Generally, a CMOS (complementary metal oxide semiconductor) transistor comprises a semiconductor substrate on which N-channel MOS transistors and P-channel MOS transistors are formed. The semiconductor substrate is provided with active areas that are separated by either a LOCOS (localized oxidation of silicon) or a trench isolation method. N and P-type impurities are doped into the active areas to form N and P-wells. P-channel transistors are then formed on the N-wells while N-channel transistors are formed on the P-wells.
In the above described CMOS transistor manufacturing method, several lithographic masking steps are required in forming the N and P-wells. At least two lithographic masking steps are necessary for masking N-well regions when doping the P-type impurities on P-well regions and for masking the P-well regions when doping the N-type impurities on the N-well regions. The same lithographic masking steps are applied when forming the N and P-channel transistors.
Multiple lithographic masking steps are time-consuming and cause mask alignment errors, thereby deteriorating yield as well as increasing manufacturing costs. In an attempt to solve the above drawbacks, a method for making a dual-well CMOS transistor using only a single lithographic masking step has been developed. U.S. Pat. Nos. 4,558,508, 4,144,101, and 4,435,896 disclose such a method.